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1 of 59 may 25, 2004 ? 2004 integrated device technology, inc. dsc 6148 idt and the idt logo are registered trademar ks of integrated device technology, inc. features 32-bit cpu core ? mips32 instruction set ? cache sizes: 16kb instruction and data caches, 4-way set associative, cache line lo cking, non-blocking prefetches ? 16 dual-entry jtlb with variable page sizes ? 3-entry instruction tlb ? 3-entry data tlb ? max issue rate of one 32x16 multiply per clock ? max issue rate of one 32x32 multiply every other clock ? cpu control with start, stop and single stepping ? software breakpoints support ? hardware breakpoints on virtual addresses ? enhanced jtag and ice interface t hat is compatible with v2.5 of the ejtag specification ddr memory controller ? supports up to 2gb of ddr sdram ? 2 chip selects (each chip select supports 4 internal ddr banks) ? supports 16-bit or 32-bit data bus width using 8, 16, or 32-bit devices ? supports 64mb, 128mb, 256mb, 512mb, and 1gb ddr sdram devices ? data bus multiplexing support allows interfacing to standard ddr dimms and sodimms ? automatic refresh generation memory and peripheral device controller ? provides ?glueless? interface to standard sram, flash, rom, dual-port memory, and peripheral devices ? demultiplexed address and data bus es: 16-bit data bus, 26-bit address bus, 6 chip selects, supports alternate bus masters, control for external data bus buffers ? supports 8-bit and 16-bit width devices automatic byte gathering and scattering ? flexible protocol configurat ion parameters: programmable number of wait states (0 to 63), programmable postread/post- write delay (0 to 31), supports external wait state generation, supports intel and motorola style peripherals ? write protect capability per chip select ? programmable bus transaction timer generates warm reset when counter expires ? supports up to 64 mb of memory per chip select counter/timers ? three general purpose 32- bit counter timers pci interface ? 32-bit pci revision 2.2 compliant (3.3v only) ? supports host or satellite operation in both master and target modes ? support for synchronous and asynchronous operation ? pci clock supports frequencie s from 16 mhz to 66 mhz ? pci arbiter in host mode: suppor ts 6 external masters, fixed priority or round robin arbitration ?i 2 o ?like? pci messaging unit block diagram ejtag mmu d. cache i. cache mips-32 cpu core ice interrupt controller 3 counter timers dma controller arbiter ddr ddr & device 2 uarts (16550) gpio interface pci master/target memory & peripheral bus ch. 1 ch. 2 serial channels gpio pins pci bus controller controller spi i 2 c spi bus i 2 c bus : : 10/100 2 ethernet interfaces mii mii ipbus tm interface pci arbiter (host mode) controllers on-chip memory 79rc32438 idt tm interprise tm integrated communications processor
2 of 59 may 25, 2004 idt 79rc32438 dma controller ? 10 dma channels: two channels for pci (pci to memory and memory to pci), two for each ethernet interface, two channels for memory to memory operat ions, two channels for external operations ? provides flexible descriptor based operation ? supports unaligned transfers (i .e., source or destination address may be on any byte boundar y) with arbitrary byte length. two ethernet interfaces ? 10 and 100 mb/s iso/iec 8802-3:1996 compliant ? two ieee 802.3u compatible media independent interfaces (mii) with serial management interface ? mii supports ieee 802.3u auto-negotiation speed selection ? supports 64 entry hash table based multicast address filtering ? 512 byte transmit and receive fifos ? supports flow control functions outlined in ieee std. 802.3x- 1997 universal asynchronous r eceiver transmitter (uart) ? compatible with the 16550 and 16450 uarts ? two completely separate serial channels ? modem control functions (cts, rts, dsr, dtr, ri, dcd) ? 16-byte transmit and receive buffers ? programmable baud rate generator derived from the system clock ? fully programmable se rial characteristics: ? 5, 6, 7, or 8 bit characters ? even, odd or no parity bit generation and detection ? 1, 1-1/2 or 2 stop bit generation ? line break generation and detection ? false start bit detection ? internal loopback mode i 2 c-bus ? supports standard 100 kbps mode as well as 400 kbps fast mode ? supports 7-bit and 10-bit addressing ? supports four modes: master transmitter, master receiver, slave transmitter, slave receiver additional general purpose peripherals ? two 16550-compatible serial ports ? interrupt controller ? system integrity functions ? general purpose i/o controller ? serial peripheral interface (spi) on-chip memory ? 4kb of high speed sram organized as 1k x 32 bits ? supports burst and non-burst byte , halfword, triple-byte, and word cpu, pci, and dma accesses debug support ? rev. 2.6 compliant ejtag interface device overview the rc32438 is a member of the idt? interprise? family of pci integrated communications processo rs. it incorporates a high perfor- mance cpu core and a number of on- chip peripherals. the integrated processor is designed to transfer info rmation from i/o modules to main memory with minimal cpu interv ention using a highly sophisticated direct memory access (dma) engine. all data transfers through the rc32438 are achieved by writing data from an on-chip i/o peripheral to main memory and then out to another i/o module. cpu execution core the 32-bit cpu core is 100% compatible with the mips32 instruction set architecture (isa). specifically, this device features the 4kc cpu core developed by mips technologies inc. (www.mips. com). this core issues a single instruction per cycle, includes a fi ve stage pipeline, and is optimized for applications that require integer ar ithmetic. the cpu core includes 16 kb instruction and 16 kb data caches. both caches are 4-way set asso- ciative and can be locked on a per line basis, which allows the programmer control over this preci ous on-chip memory resource. the core also features a memory management unit (mmu). the cpu core also incorporates an enhanced joint test access group (ejtag) inter- face that is used to interface to in-circuit emulator tools, providing access to internal registers and enabl ing the part to be controlled exter- nally, simplifying the system debug process. the use of this core allows idt's customers to leverage the broad range of software and develop- ment tools available for the mips architecture, including operating systems, compilers, and in -circuit emulators. double data rate memory controller the rc32438 incorporates a high performance double data rate (ddr) memory controller whic h supports both x16 and x32 memory configurations up to 2gb. this module provides all of the signals required to interface to both me mory modules and discrete devices, including two chip selects, differential clocking outputs and data strobes. memory and i/o controller the rc32438 uses a dedicated local memory/io controller including a de-multiplexed 16-bit data and 26-bit address bus. it includes all of the signals required to interface directly to as many as six intel or motorola- style external peripherals, and t he interface can be configured to support both 8-bit and 16-bit peripherals. dma controller the dma controller consists of 10 independent dma channels, all of which operate in exactly the same manner. the dma controller off-loads the cpu core from moving data among the on-chip interfaces, external peripherals, and memory. the contro ller supports scatter/gather dma with no alignment restrictions, appropriate for communications and graphics systems. pci interface the pci interface on the rc32438 is compatible with version 2.2 of the pci specification. an on-chip ar biter supports up to six external bus masters, supporting both fixed priori ty and rotating priority arbitration schemes. the part can support both satellite and host pci configura- tions, enabling the rc32438 to act as a slave controller for a pci add-in
3 of 59 may 25, 2004 idt 79rc32438 card application, or as the primary pc i controller in th e system. the pci interface can be operated synchronousl y or asynchronously to the other i/o interfaces on the rc32438 device. ethernet interface the rc32438 has two ethernet channels supporting 10mbps and 100mbps speeds to provide a st andard media independent interface (mii) off-chip, allowing a wide range of external devices to be connected efficiently. uart interface the rc32438 contains two comple tely separate serial channels (uarts) that are compatible with the industry standard 16550 uart. system integrity functions the rc32438 contains a programm able watchdog timer that gener- ates nmi when the counter expires and an address space monitor that reports errors in response to accesses to undecoded address regions. general purpose i/o controller the rc32438 contains 32 general purpose input/output pins. each pin may be used as an active high or active low level interrupt or non- maskable interrupt input, and each si gnal may be used as a bit input or output port. i 2 c interface the standard i2c interface allows the rc32438 to connect to a number of standard external peripher als for a more complete system solution. the rc32438 supports bot h master and slave operations. debug support the rc32438 supports the industry standard rev. 2.6 ejtag inter- face. thermal considerations the rc32438 consumes less than 2.7 w peak power. it is guaran- teed in a ambient temperature range of 0 to +70 c for commercial temperature devices and - 40 to +85 for industrial temperature devices. revision history november 7, 2002 : initial publication. preliminary information. november 15, 2002 : added footnotes to tables 5, 9, and 10. december 12, 2002 : added clock speed parameter to pll and core supply in table 16. december 19, 2002 : release version. january 13, 2003 : changed thermal considerations to read less than 2.7w instead of 2.5w, added values to clk parameter in table 5, and revised ejtag description. february 4, 2003 : revised description for ejtag/jtag pins in table 1. changed ddrdm[7:0] from input/output to output only in tables 1 and 2 and logic diagram. added new section, voltage sense signal timing, as part of ejtag description. march 4, 2003 : in table 2, removed ?pull-up? from pci pin category and from gpio [24] and gpio[30-26]. in table 20, changed max. values for vccsi/o, vcccore, and vccpll. july 9, 2003 : in table 7: changed values for ddrdata, ddrdm, and ddraddr?wen signals, and deleted old footnote #3 and changed values in new footnote #3. in table 8, changed tdo values. changed figure 7. changed values in table 18, power consumption. removed ipbus monitor feature which included changes to tables 1, 2, 21, 24, and 25. deleted table 13 which resulted in a re-ordering of subsequent tables. march 8, 2004 : added 300mhz speed grade. may 25, 2004 : in table 9, signals miixrxclk and miixtxclk, the min and max values for thigh/tlow_9c were changed to 140 and 260 respectively and the min and max values for thigh/tlow_9d were changed to 14.0 and 26.0 respectively.
4 of 59 may 25, 2004 idt 79rc32438 pin description table the following table lists the functions of the pins provided on the rc32438. some of the functions listed may be multiplexed on to the same pin. the active polarity of a signal is defined using a suffix. si gnals ending with an ?n? are defined as being active, or asserted, when at a logic zero (low) level. all other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level. signal type name/description system clk i master clock. this is the master clock input. the processor frequency is a mul- tiple of this clock frequency. this clock is used as the system clock for all mem- ory and peripheral bus operations. extclk o external clock. this clock is used for all memory and peripheral bus opera- tions. coldrstn i cold reset. the assertion of this signal initiates a cold reset. this causes the processor state to be initialized, boot configuration to be loaded, and the internal pll to lock onto the master clock (clk). rstn i/o reset. the assertion of this bidirectional signal initiates a warm reset. this sig- nal is asserted by the rc32438 during a warm reset. memory and peripheral bus bdirn o external buffer direction. memory and peripheral bus external data bus buffer direction control. if the rc32438 memory and peripheral bus is connected to the a side of a transceiver, such as an idt74fct245, then this pin may be directly connected to the direction control (e.g., bdir) pin of the transceiver. bgn o bus grant. this signal is asserted by the rc32438 to indicate that the rc32438 has relinquished ownership of the memory and peripheral bus. boen o external buffer enable. this signal provides an output enable control for an external buffer on the memory and peripheral data bus. brn i bus request. this signal is asserted by an external device to request owner- ship of the memory and peripheral bus. bwen[1:0] o byte write enables. these signals are memory and peripheral bus byte write enable signals. bwen[0] corresponds to byte lane mdata[7:0] bwen[1] corresponds to byte lane mdata[15:8] csn[5:0] o chip selects. these signals are used to select an external device on the mem- ory and peripheral bus. maddr[21:0] o address bus. 22-bit memory and peripheral bus address bus. maddr[25:22] are available as gpio alternate functions mdata[15:0] i/o data bus. 16-bit memory and peripheral data bus. during a cold reset, these pins function as inputs that are used to load the boot configuration vector. oen o output enable. this signal is asserted when data should be driven on by an external device on the memory and peripheral bus. rwn o read write. this signal indicates if the transaction on the memory and periph- eral bus is a read transaction or a write transaction. a high level indicates a read from an external device. a low level indicates a write to an external device. table 1 pin description (part 1 of 9)
5 of 59 may 25, 2004 idt 79rc32438 waitackn i wait or transfer acknowledge. when configured as wait, this signal is asserted during a memory and peripheral bus transaction to extend the bus cycle. when configured as a transfer acknowledge, this signal is asserted during a transaction to signal the completion of the transaction. ddr bus ddraddr[13:0] o ddr address bus. 14-bit multiplexed ddr bus address bus. this bus is used to transfer the addresses to the ddr devices. ddrba[1:0] o ddr bank address. these signals are used to transfer the bank address to the ddrs. ddrcasn o ddr column address strobe. this signal is asserted during ddr transac- tions. ddrcke o ddr clock enable. the ddr clock enable is asserted during normal ddr operation. this signal is negated during following a cold reset or during a power down operation. ddrckn[1:0] o ddr negative ddr clock. these signals are the negative clock of the differen- tial ddr clock pair. two copies of this output are provided to reduce signal load- ing. ddrckp[1:0] o ddr positive ddr clock. these signals are the positive clock of the differen- tial ddr clock pair. two copies of this output are provided to reduce signal load- ing. ddrcsn[1:0] o ddr chip selects. these active low signals are used to select ddr device(s) on the ddr bus. ddrdata[31:0] i/o ddr data bus. 32-bit ddr data bus used to transfer data between the rc32438 and the ddr devices. data is transferred on both edges of the clock. ddrdm[7:0] o ddr data write enables. byte data write enables used to enable specific byte lanes during ddr writes. ddrdm[0] corresponds to ddrdata[7:0] ddrdm[1] corresponds to ddrdata[15:8] ddrdm[2] corresponds to ddrdata[23:16] ddrdm[3] corresponds to ddrdata[31:24] ddrdm[4] corresponds to ddrdata[39:32] ddrdm[5] corresponds to ddrdata[47:40] ddrdm[6] corresponds to ddrdata[55:48] ddrdm[7] corresponds to ddrdata[54:56] (refer to the ddr data bus multiplexing section in chapter 7 of the rc32438 user reference manual.) ddrdqs[3:0] i/o ddr data strobes. ddr byte data strobes used to clock data between ddr devices and the rc32438. these strobes are inputs during ddr reads and out- puts during ddr writes. ddrdqs[0] corresponds to ddrdata[7:0]. ddrdqs[1] corresponds to ddrdata[15:8]. ddrdqs[2] corresponds to ddrdata[23:16]. ddrdqs[3] corresponds to ddrdata[31:24]. ddroen[3:0] o ddr bus switch output enables. these pins are used to enable external data bus switches in systems that support data bus multiplexing. ddrrasn o ddr row address strobe. the ddr row address strobe is asserted during ddr transactions. signal type name/description table 1 pin description (part 2 of 9)
6 of 59 may 25, 2004 idt 79rc32438 ddrvref i ddr voltage reference. sstl_2 ddr voltage reference generated by an external source. ddrwen o ddr write enable. ddr write enable is asserted during ddr write transac- tions. pci bus pciad[31:0] i/o pci multiplexed address/data bus . address is driven by a bus master during initial pciframen assertion. data is then driven by the bus master during writes or by the bus target during reads. pcicben[3:0] i/o pci multiplexed command/byte enable bus . pci command is driven by the bus master during the initial pciframen assertion. byte enable signals are driven by the bus master during subsequent data phase(s). pciclk i pci clock . clock used for all pci bus transactions. pcidevseln i/o pci device select . this signal is driven by a bus target to indicate that the tar- get has decoded the address as one of its own address spaces. pciframen i/o pci frame . driven by a bus master. assertion indicates the beginning of a bus transaction. negation indicates the last data. pcigntn[3:0] i/o pci bus grant . in pci host mode with internal arbiter: the assertion of these signals indicates to the agent that the internal rc32438 arbiter has granted the agent access to the pci bus. in pci host mode with external arbiter: pcigntn[0]: asserted by an external arbiter to indicate to the rc32438 that access to the pci bus has been granted. pcigntn[3:1]: unused and driven high. in pci satellite mode: pcigntn[0]: this signal is asserted by an external arbiter to indicate to the rc32438 that access to the pci bus has been granted. pcigntn[1]: this signal takes on the alternate function of pcieecs and is used as a pci serial e eprom chip select pcigntn[3:2]: unused and driven high. note : when the gpio register is programmed in the alternate function mode for bits gpio [26] and [28], these bits become pcigntn [4] and [5] respectively. pciirdyn i/o pci initiator ready . driven by the bus master to indicate that the current datum can complete. pcilockn i/o pci lock . this signal is asserted by an external bus master to indicate that an exclusive operation is occurring. pcipar i/o pci parity . even parity of the pciad[31:0] bus. driven by the bus master during address and write data phases. driven by the bus target during the read data phase. pciperrn i/o pci parity error . if a parity error is detected, this signal is asserted by the receiving bus agent 2 clocks after the data is received. signal type name/description table 1 pin description (part 3 of 9)
7 of 59 may 25, 2004 idt 79rc32438 pcireqn[3:0] i/o pci bus request. in pci host mode with internal arbiter: these signals are inputs whose assertion indicates to the internal rc32438 arbiter that an agent desires ownership of the pci bus. in pci host mode with external arbiter: pcireqn[0]: asserted by the rc32438 to request ownership of the pci bus. pcireqn[3:1]: unused and driven high. in pci satellite mode: pcireqn[0]: this signal is asserted by the rc32438 to request use of the pci bus. pcireqn[1]: function changes to pciidsel and is used as a chip select during configuration read and write transactions. pcireqn[3:2]: unused and driven high. note : when the gpio register is programmed in the alternate function mode for bits gpio [24] and [27], these bits become pcireqn [4] and [5] respectively. pcirstn i/o pci reset . in host mode, this signal is asserted by the rc32438 to generate a pci reset. in satellite mode, assertion of this signal initiates a warm reset. pciserrn i/o pci system error . this signal is driven by an agent to indicate an address par- ity error, data parity error during a special cycle command, or any other system error. requires an external pull-up. pcistopn i/o pci stop . driven by the bus target to terminate the current bus transaction. for example, to indicate a retry. pcitrdyn i/o pci target ready . driven by the bus target to indicate that the current data can complete. general purpose input/output gpio[0] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0sout alternate function: uart channel 0 serial output. gpio[1] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0sinp alternate function: uart channel 0 serial input. gpio[2] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0rin alternate function: uart channel 0 ring indicator input. gpio[3] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0dcdn alternate function: uart channel 0 data carrier detect input. gpio[4] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0dtrn alternate function: uart channel 0 data terminal ready input. gpio[5] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0dsrn alternate function: uart channel 0 data set ready input. signal type name/description table 1 pin description (part 4 of 9)
8 of 59 may 25, 2004 idt 79rc32438 gpio[6] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0rtsn alternate function: uart channel 0 request to send output. gpio[7] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u0ctsn alternate function: uart channel 0 clear to send input. gpio[8] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u1sout alternate function: uart channel 1 serial output. gpio[9] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u1sinp alternate function: uart channel 1 serial input. gpio[10] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u1dtrn alternate function: uart channel 1 data terminal ready output. gpio[11] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u1dsrn alternate function: uart channel 1 data set ready input. gpio[12] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u1rtsn alternate function: uart channel 1 request to send output. gpio[13] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: u1ctsn alternate function: uart channel 1 clear to send input. gpio[14] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: dmareqn0 alternate function: external dma channel 0 request input. gpio[15] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: dmareqn1 alternate function: external dma channel 1 request input. gpio[16] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: dmadonen0 alternate function: external dma channel 0 done input. gpio[17] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: dmadonen1 alternate function: external dma channel 1 done input. signal type name/description table 1 pin description (part 5 of 9)
9 of 59 may 25, 2004 idt 79rc32438 gpio[18] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: dmafinn0 alternate function: external dma channel 0 finished output. gpio[19] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: dmafinn1 alternate function: external dma channel 1 finished output. gpio[20] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin alternate function pin name: maddr[22] alternate function: memory and peripheral bus address output. gpio[21] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: maddr[23] alternate function: memory and peripheral bus address output. gpio[22] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: maddr[24] alternate function: memory and peripheral bus address output. gpio[23] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: maddr[25] alternate function: memory and peripheral bus address output. gpio[24] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcireqn[4] alternate function: pci request 4 input or output. gpio[25] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: afspare1 alternate function: reserved. gpio[26] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcigntn[4] alternate function: pci grant 4 output. gpio[27] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcireqn[5] alternate function: pci request 5 input or output. gpio[28] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcigntn[5] alternate function: pci grant 5 output. gpio[29] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: reserved alternate function: reserved. signal type name/description table 1 pin description (part 6 of 9)
10 of 59 may 25, 2004 idt 79rc32438 gpio[30] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. alternate function pin name: pcimuintn alternate function: pci messaging unit interrupt output. gpio[31] i/o general purpose i/o. this pin can be configured as a general purpose i/o pin. spi interface sck i/o serial clock . this signal is used as the serial clock output in spi mode and in pci satellite mode with suspended cpu ex ecution during pc i serial eeprom loading. this pin may be configured as a gpio pin. sdi i/o serial data input . this signal is used to shift in serial data in spi mode and in pci satellite mode with suspended cpu ex ecution during pc i serial eeprom loading. this pin may be configured as a gpio pin. sdo i/o serial data output . this signal is used shift out serial data in spi mode and in pci satellite mode with suspended cpu ex ecution during pc i serial eeprom loading. this pin may be configured as a gpio pin. i 2 c bus interface scl i/o i 2 c clock. i 2 c-bus clock. sda i/o i 2 c data bus. i 2 c-bus data bus. ethernet interfaces mii0cl i ethernet 0 mii collision detected. this signal is asserted by the ethernet phy when a collision is detected. mii0crs i ethernet 0 mii carrier sense. this signal is asserted by the ethernet phy when either the transmit or receive medium is not idle. mii0rxclk i ethernet 0 mii receive clock. this clock is a continuous clock that provides a timing reference for the reception of data. mii0rxd[3:0] i ethernet 0 mii receive data. this nibble wide data bus contains the data received by the ethernet phy. mii0rxdv i ethernet 0 mii receive data valid. the assertion of this signal indicates that valid receive data is in the mii receive data bus. mii0rxer i ethernet 0 mii receive error. the assertion of this signal indicates that an error was detected somewhere in the ethernet frame currently being sent in the mii receive data bus. mii0txclk i ethernet 0 mii transmit clock. this clock is a continuous clock that provides a timing reference for the transfer of transmit data. mii0txd[3:0] o ethernet 0 mii transmit data. this nibble wide data bus contains the data to be transmitted. mii0txenp o ethernet 0 mii transmit enable. the assertion of this signal indicates that data is present on the mii for transmission. mii0txer o ethernet 0 mii transmit coding error. when this signal is asserted together with miitxenp, the ethernet phy will transmit symbols which are not valid data or delimiters. mii1cl i ethernet 1 mii collision detected. this signal is asserted by the ethernet phy when a collision is detected. signal type name/description table 1 pin description (part 7 of 9)
11 of 59 may 25, 2004 idt 79rc32438 mii1crs i ethernet 1 mii carrier sense. this signal is asserted by the ethernet phy when either the transmit or receive medium is not idle. mii1rxclk i ethernet 1 mii receive clock. this clock is a continuous clock that provides a timing reference for the reception of data. mii1rxd[3:0] i ethernet 1 mii receive data. this nibble wide data bus contains the data received by the ethernet phy. mii1rxdv i ethernet 1 mii receive data valid. the assertion of this signal indicates that valid receive data is in the mii receive data bus. mii1rxer i ethernet 1 mii receive error. the assertion of this signal indicates that an error was detected somewhere in the ethernet frame currently being sent in the mii receive data bus. mii1txclk i ethernet 1 mii transmit clock. this clock is a continuous clock that provides a timing reference for the transfer of transmit data. mii1txd[3:0] o ethernet 1 mii transmit data. this nibble wide data bus contains the data to be transmitted. mii1txenp o ethernet 1 mii transmit enable. the assertion of this signal indicates that data is present on the mii for transmission. mii1txer o ethernet 1 mii transmit coding error. when this signal is asserted together with miitxenp, the ethernet phy will transmit symbols which are not valid data or delimiters. miimdc o mii management data clock. this signal is used as a timing reference for transmission of data on the management interface. miimdio i/o mii management data. this bidirectional signal is used to transfer data between the station management entity and the ethernet phy. jtag / ejtag ejtag_tms i ejtag mode . the value on this signal controls the test mode select of the ejtag controller. when using the jtag boundary scan, this pin should be left disconnected (since there is an internal pull-up) or driven high. jtag_tck i jtag clock . this is an input test clock used to clock the shifting of data into or out of the boundary scan logic, jtag controller, or the ejtag controller. jtag_tck is independent of the system and the processor clock with a nomi- nal 50% duty cycle. jtag_tdi i jtag data input . this is the serial data input to the boundary scan logic, jtag controller, or the ejtag controller. jtag_tdo o jtag data output . this is the serial data shifted out from the boundary scan logic, jtag controller, or the ejtag controller. when no data is being shifted out, this signal is tri-stated. jtag_tms i jtag mode . the value on this signal controls the test mode select of the boundary scan logic or jtag controller. when using the ejtag debug inter- face, this pin should be left disconnected (since there is an internal pull-up) or driven high. signal type name/description table 1 pin description (part 8 of 9)
12 of 59 may 25, 2004 idt 79rc32438 pin characteristics note: some input pads of the rc32438 do not contain internal pull-ups or pull-downs. unused inputs s hould be tied off to appropriate levels. this is especially critical for un used control signal inputs (such as brn) whic h, if left floating, could adversely aff ect the rc32438?s operation. also, any input pin left floating can cause a slight increase in power consumption. jtag_trst_n i jtag reset . this active low signal asynchronously resets the boundary scan logic, jtag tap controller, and the ejtag debug tap controller. an external pull-up on the board is recommended to meet the jtag specification in cases where the tester can access this signal. however, for systems running in func- tional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board 3) clock jtag_tck while holding ejtag_tms and/or jtag_tms high. debug cpu o cpu transaction. this signal is asserted during all cpu instruction fetches and data transfers to/from the ddr and devices on the memory and peripheral bus. the signal is negated during pci and dma transactions to/from the ddr and devices on the memory and peripheral bus. inst o instruction or data. this signal is driven high during cpu instruction fetches on the memory and peripheral bus memory or ddr bus. function pin name type buffer i/o type internal resistor notes 1 memory and peripheral bus bdirn o lvttl high drive bgn o lvttl low drive boen o lvttl high drive brn i lvttl sti 2 pull-up bwen[1:0] o lvttl high drive csn[5:0] o lvttl high drive maddr[21:0] o lvttl high drive mdata[15:0] i/o lvttl high drive oen o lvttl high drive rwn o lvttl high drive waitackn i lvttl sti pull-up table 2 pin characteristics (part 1 of 4) signal type name/description table 1 pin description (part 9 of 9)
13 of 59 may 25, 2004 idt 79rc32438 ddr bus ddraddr[13:0] o sstl_2 sstl_2 ddrba[1:0] o sstl_2 sstl_2 ddrcasn o sstl_2 sstl_2 ddrcke o sstl_2 / lvcmos sstl_2 ddrckn[1:0] o sstl_2 sstl_2 ddrckp[1:0] o sstl_2 sstl_2 ddrcsn[1:0] o sstl_2 sstl_2 ddrdata[31:0] i/o sstl_2 sstl_2 ddrdm[7:0] o sstl_2 sstl_2 ddrdqs[3:0] i/o sstl_2 sstl_2 ddroen[3:0] o sstl_2 sstl_2 ddrrasn o sstl_2 sstl_2 ddrvref i analog sstl_2 ddrwen o sstl_2 sstl_2 pci bus interface 3 pciad[31:0] i/o pci pci pcicben[3:0] i/o pci pci pciclk i pci pci pcidevseln i/o pci pci pull-up on board pciframen i/o pci pci pull-up on board pcigntn[3:0] i/o pci pci pull-up on board pciirdyn i/o pci pci pull-up on board pcilockn i/o pci pci pcipar i/o pci pci pciperrn i/o pci pci pcireqn[3:0] i/o pci pci pull-up on board pcirstn i/o pci pci pull-down on board pciserrn i/o pci open collec- tor; pci pull-up on board pcistopn i/o pci pci pull-up on board pcitrdyn i/o pci pci pull-up on board general purpose i/o gpio[23:0] i/o lvttl low drive pull-up gpio[24] i/o pci pull-up on board gpio[25] i/o lvttl low drive pull-up gpio[30:26] 4 i/o pci pull-up on board gpio[31] i/o lvttl low drive pull-up function pin name type buffer i/o type internal resistor notes 1 table 2 pin characteristics (part 2 of 4)
14 of 59 may 25, 2004 idt 79rc32438 serial interface sck i/o lvttl low drive pull-up pull-up on board sdi i/o lvttl low drive pull-up pull-up on board sdo i/o lvttl low drive pull-up pull-up on board i 2 c-bus interface scl i/o lvttl low drive/sti pull-up on board 5 sda i/o lvttl low drive/sti pull-up on board 5 ethernet interfaces mii0cl i lvttl sti pull-down mii0crs i lvttl sti pull-down mii0rxclk i lvttl sti pull-up mii0rxd[3:0] i lvttl sti pull-up mii0rxdv i lvttl sti pull-down mii0rxer i lvttl sti pull-down mii0txclk i lvttl sti pull-up mii0txd[3:0] o lvttl low drive mii0txenp o lvttl low drive mii0txer o lvttl low drive mii1cl i lvttl sti pull-down mii1crs i lvttl sti pull-down mii1rxclk i lvttl sti pull-up mii1rxd[3:0] i lvttl sti pull-up mii1rxdv i lvttl sti pull-down mii1rxer i lvttl sti pull-down mii1txclk i lvttl sti pull-up mii1txd[3:0] o lvttl low drive mii1txenp o lvttl low drive mii1txer o lvttl low drive miimdc o lvttl low drive miimdio i/o lvttl low drive pull-up ejtag / ice jtag_trst_n i lvttl sti pull-up jtag_tck i lvttl sti pull-up jtag_tdi i lvttl sti pull-up jtag_tdo o lvttl low drive jtag_tms i lvttl sti pull-up ejtag_tms i lvttl sti pull-up debug cpu o lvttl low drive inst o lvttl low drive function pin name type buffer i/o type internal resistor notes 1 table 2 pin characteristics (part 3 of 4)
15 of 59 may 25, 2004 idt 79rc32438 boot configuration vector the boot configuration vector is read by the rc32438 during a cold reset. the vector defines essential rc32438 parameters that are required once the cold reset completes. the encoding of the boot configuration vector is described in table 3, and the vector input is illustrated in figure 4. the val ue of the boot configura- tion vector read in by the rc32438 during a cold reset may be deter mined by reading the boot confi guration vector (bcv) registe r. miscellaneous clk i lvttl sti extclk o lvttl high drive coldrstn i lvttl sti rstn i/o lvttl low drive / sti pull-up pull-up on board 1. external pull-up required in most system applications. some applications may require additional pull-ups not identified in this table. 2. schmidt trigger input (sti). 3. the pci pins have internal pull-ups but they are too weak to guarantee system validity. therefore, board pull-ups are mandatory where indicated. gpio alternate function pi ns for pci must also have board pull-ups. 4. pcimuintn is an alternate function of gpio[30]. when configured as an alternate function, this pin is tri-stated when not asser ted (i.e., it acts as an open collector output). 5. use a 2.2k pull-up resistor for i2c pins. signal name/description mdata[3:0] cpu pipeline clock multiplier . this field specifies the value by which the pll multi- plies the master clock input (clk) to obtain the processor clock frequency (pclk). for master clock input frequency constraints, refer to table 3.1 in the rc32438 user man- ual. 0x0 - pll bypass 0x1 - multiply by 3 0x2 - multiply by 4 0x3 - multiply by 6 0x4 - multiply by 8 0x5 - reserved 0x6 - reserved 0x7 - reserved 0x8 - reserved 0xd - reserved 0xe - reserved 0xf - reserved mdata[5:4] external clock divider . this field specifies the value by which the ipbus clock (iclk), which is always 1/2 pclk, is divided in order to generate the external clock output on the extclk pin. 0x0 - divide by 1 0x1 - divide by 2 0x2 - divide by 4 0x3 - reserved mdata[6] endian. this bit specifies the endianness. 0x0 - little endian 0x1 - big endian table 3 boot configuration encoding (part 1 of 2) function pin name type buffer i/o type internal resistor notes 1 table 2 pin characteristics (part 4 of 4)
16 of 59 may 25, 2004 idt 79rc32438 mdata[7] boot device width . this field specifies the width of the boot device (i.e., device 0). 0x0 - 8-bit boot device width 0x1 - 16-bit boot device width mdata[8] reset mode . this bit specifies the length of time the rstn signal is driven. 0x0 - normal reset: rstn driven for minimum of 4096 clock cycles 0x1 - reserved mdata[11:9] pci mode . this bit controls the operating mode of the pci bus interface. the initial value of the en bit in the pcic register is determined by the pci mode. 0x0 - disabled (en initial value is zero) 0x1 - pci satellite mode with pci target not ready (en initial value is one) 0x2 - pci satellite mode with suspended cpu execution (en initial value is one) 0x3 - pci host mode with external arbiter (en initial value is zero) 0x4 - pci host mode with internal arbiter using fixed priority arbitration algorithm (en initial value is zero) 0x5 - pci host mode with internal arbiter using round robin arbitration algorithm (en initial value is zero) 0x6 - reserved 0x7 - reserved mdata[12] disable watchdog timer . when this bit is set, the watchdog timer is disabled follow- ing a cold reset. 0x0 - watchdog timer enabled 0x1 - watchdog timer disabled mdata[15:13] reserved . these pins must be driven low during boot configuration. signal name/description table 3 boot configuration encoding (part 2 of 2)
17 of 59 may 25, 2004 idt 79rc32438 logic diagram ? rc32438 figure 1 logic diagram miscellaneous signals memory and peripheral bus clk coldrstn rstn 4 miimdc miimdio mii0cl mii0crs mii0rxclk mii0rxd[3:0] mii0rxdv mii0rxer mii0txclk mii0txd[3:0] mii0txenp mii0txer mii1cl mii1crs mii1rxclk mii1rxd[3:0] mii1rxdv mii1rxer mii1txclk mii1txd[3:0] mii1txenp mii1txer bdirn bgn boen brn bwen[1:0] csn[5:0] maddr[21:0] mdata[15:0] oen rwn waitackn ddraddr[13:0] ddrba[1:0] ddrcasn ddrcke ddrckn[1:0] ddrckp[1:0] ddrcsn[1:0] ddrdata[31:0] ddrdm[7:0] ddrdqs[3:0] ddrrasn ddrvref ddrwen pciad[31:0] pcicben[3:0] pciclk pcidevseln pciframen pcigntn[3:0] pciirdyn pcilockn pcipar pciperrn pcireqn[3:0] pcirstn pciserrn pcistopn pcitrdyn gpio[31:0] sdo sda scl jtag_tck jtag_tdi jtag_tdo jtag_tms jtag_trst_n inst cpu 4 4 4 32 4 4 4 32 4 8 32 2 2 2 2 14 16 22 6 2 ejtag / jtag signals debug signals general purpose i/o i 2 c-bus serial i/o pci bus ddr bus ethernet rc32438 vcccore vcci/o vss vccpll vsspll power/ground sdi sck ddroen[3:0] 4 ejtag_tms extclk
18 of 59 may 25, 2004 idt 79rc32438 ac timing definitions below are examples of the ac timing char acteristics used throughout this document. figure 2 ac timing definitions waveform symbol definition tper clock period. tlow clock low. amount of time the clock is low in one clock period. thigh clock high. amount of time the clock is high in one clock period. trise rise time. low to high transition time. tfall fall time. high to low transition time. tjitter jitter. amount of time the reference clock (or signal) edge can vary on either the rising or falling edges. tdo data out. amount of time after the reference clock edge that the output will become valid. the minimum time represents the d ata output hold. the maximum time represents the earliest time the designer can use the data. tzd z state to data valid. amount of time after the reference clock edge that the tri-stated output takes to become valid. tdz data valid to z state. amount of time after the reference clock edge that the valid output takes to become tri-stated. tsu input set-up. amount of time before the reference clock edge that the input must be valid. thld input hold. amount of time after the reference clock edge that the input must remain valid. tpw pulse width. amount of time the input or output is active for asynchronous signals. tslew slew rate. the rise or fall rate for a signal to go from a high to low, or low to high. x(clock) timing value. this notation represents a value of ?x? multiplied by the clock time period of the specified clock. using 5(clk) as an example: x = 5 and the oscillator clock (clk) = 25mhz, then the timing value is 200. tskew skew. the amount of time two signal edges deviate from one another. table 4 ac timing definitions tdz tzd tdo tpw tpw thld tsu tlow thigh thigh tper clock output signal 1 output signal 2 input signal 1 signal 1 tjitter trise tfall tdo signal 2 signal 3 tskew
19 of 59 may 25, 2004 idt 79rc32438 system clock parameters values based on systems running at recommended supply voltages and operating temperatures, as shown in tables 15 and 16. figure 3 clock parameters waveform parameter symbol reference edge 200mhz 233mhz 266mhz 300mhz units timing diagram reference minmaxminmaxminmaxminmax pclk 1 1. the cpu pipeline clock (pclk) speed is selected during cold reset by the boot configuration vect or (see table 3). frequency none 200 200 200 233 200 266 200 300 mhz see figure 3. tper 5.0 5.0 4.2 5.0 3.8 5.0 3.3 5.0 ns iclk 2,3,4 2. iclk is the internal ipbus clock. it is always equal to pclk divided by 2. this clock cannot be sampled externally. 3. the ethernet clock (miixrxclk and miixtxclk) frequency must be equal to or less than 1/2 iclk (miixrxclk and miixtxclk <= 1/2(i clk)). 4. pciclk must be equal to or less than two times iclk (pciclk <= 2(iclk)) with a maximum pciclk of 66mhz. frequency none 100 100 100 116.5 100 133 100 150 mhz tper 10.0 10.0 10.0 8.5 10.0 7.5 6.7 10.0 ns clk 5 5. the input clock (clk) is input from the ex ternal oscillator to the internal pll. frequency none 25 66.6 25 77.6 25 88.6 25 100 mhz tper_5a 15.0 40.0 12.9 40.0 11.2 40.0 10 40 ns thigh_5a, tlow_5a 40 60 40 60 40 60 40 60 % of tper_5a trise_5a, tfall_5a ?3.0?3.0?3.0?3.0 ns tjitter_5a ? 0.1 ? 0.1 ? 0.1 ? 0.1 ns table 5 clock parameters tlow_5a thigh_5a tper_5a clk trise_5a tfall_5a tjitter_5a tjitter_5a
20 of 59 may 25, 2004 idt 79rc32438 ac timing characteristics values given below are based on systems running at recommended operating temperatures and supply voltages, shown in tables 15 a nd 16. figure 4 cold reset ac timing waveform signal symbol reference edge 200mhz 233mhz 266mhz 300mhz unit conditions timing diagram reference min max min max min max min max reset coldrstn 1 1. the coldrstn minimum pulse width is the oscillato r stabilization time (osc) plus 0.5 ms with v cc stable. tpw_6a 2 2. the values for this symbol were determined by calculation, not by testing. none osc + 0.5 ?osc + 0.5 ?osc + 0.5 ?osc + 0.5 ? ms cold reset see figures 4 and 5. trise_6a none ? 5.0 ? 5.0 ? 5.0 ? 5.0 ns cold reset rstn 3 (input) tpw_6b 2 none 2(clk) ? 2(clk) ? 2(clk) ? 2(clk) ?nswarm reset rstn 3 (output) 3. rstn is a bidirectional signal. it is treated as an asynchronous input. tdo_6c coldrstn falling ? 15.0 ? 15.0 ? 15.0 ? 15.0 ns cold reset mdata[15:0] (boot vector) thld_6d coldrstn rising 3.0?3.0?3.0?3.0? nscold reset tdz_6d 2 coldrstn falling ? 30.0 ? 30.0 ? 30.0 ? 30.0 ns cold reset tdz_6d 2 rstn falling ? 5(clk) ? 5(clk) ? 5(clk) ? 5(clk) ns warm reset tzd_6d 2 rstn rising 2(clk) ? 2(clk) ? 2(clk) ? 2(clk) ? ns warm reset table 6 reset and system ac timing characteristics boot vect clk coldrstn rstn mdata[15:0] bdirn boen tpw_6a >= 4096 clk clock cycles 1 2 3 4 5 6 ffff_ffff 1. coldrstn asserted by external logic. the rc32438 asserts rstn, asserts boen low, drives bdirn low, disables extc lk, and tri-states the data bus and all output pins in response. 2. external logic begins driving valid boot configuration vector on the data bus, and the rc32438 starts sampling it. 3. external logic negates coldrstn and tri-st ates the boot configur ation vector on mdata[15:0]. t he boot configuration vector mu st not be tri-stated before coldrstn is negated. the rc32438 stops sampling the boot configuration vector. 4. the rc32438 starts driving the data bus, mdata[15:0], negate s boen, drives bdirn high, and starts driving extclk. 5. rstn negated by the rc32438. 6. cpu begins executing by taking mips re set exception, and the rc32438 starts sa mpling rstn as a warm reset input. <= 16 clk clock cycles >= 4096 clk clock cycles extclk tdz_6d thld_6d trise_6a
21 of 59 may 25, 2004 idt 79rc32438 figure 5 warm reset ac timing waveform signal symbol 1 1. in the ddr data sheet: tskew_7g = t dqsq; tdo_7k = t dh , t ds; tdo_7l = t dh , t ds; tac = t ac; tdo_7m = t ih , t is. referenc e edge 200mhz 233mhz 266mhz 300mhz unit conditions timing diagram reference min max min max min max min max memory bus - ddr access ddrdata[31:0] tskew_7g 2 2. meets ddr timing requirements for ddr 266 sdrams with 400 ps remaining margin to compensate for pcb propagation mismatches, whi ch is adequate to guarantee functional timing, provided the rc32438 ddr layout guidelines are followed. ddrdqsx 0.0 0.9 0.0 0.9 0.0 0.9 0.0 0.8 ns see figures 6 and 7. tdo_7k 3 3. setup times are calculated as applicable cloc k period - tdo max. for example, if the ddr is running at 266mhz, it uses a 133mhz input clock. the period for a 133mhz clock is 7.5ns. if the tdo max value is 4.5ns, the t is parameter is 7.5ns minus 4.5ns = 3ns. the ddr spec for this parameter is 1ns, so ther e is 2ns of slack left over for board pro pagation. calculations for t ds are similar, but since this parameter is taken relative to th e ddrdqs signals, which are refer enced on both edges, the effecti ve period with a 133mhz input clock is only 3.75ns. so, if the max tdo is 2.7ns, we have 3.75ns minus 2.7ns = 1.05ns for t ds . the ddr data sheet specs a value of 0.5ns for 266mhz, so this leaves 0.55ns slack for board propagation delays. 1.5 3.3 1.1 2.9 0.9 2.7 0.7 2.4 ns ddrdm[7:0] tdo_7l ddrdqsx 1.5 3.3 1.1 2.9 0.9 2.7 0.7 2.4 ns ddrdqs[3:0] tac ddrckpx -0.75 0.75 -0.75 0.75 -0.75 0.75 -0.75 0.75 ns ddraddr[13:0], ddrba[1:0], ddrcasn, ddrcke, ddrcsn[1:0], ddroen[3:0], ddrrasn, ddrwen tdo_7m 4 ddrckpx 1.1 4.5 1.1 4.5 1.1 4.5 1.1 4.5 ns table 7 ddr sdram timing characteristics 1. warm reset caused by any of the conditions listed in the warm reset section of chapt er 3, clocking and initialization, in the rc32438 user reference manual. 2. the rc32438 tri-states the data bus, mdata[ 15:0], and negates all memory control signals. 3. the rc32438 negates rstn. 4. the rc32438 starts driving the data bus, mdata[15: 0], again, but does not sample the rstn input. 5. cpu begins executing by taking a mips soft reset exc eption and also starts sampling the rstn input again. active deasserted active clk coldrstn rstn mdata[15:0] mem control signals >= 4096 clk clock cycles >= 4096 clk clock cycles (rstn ignored during this period to allow pull-up to drive signal high) ffff_ffff 1 2 3 4 5 extclk tdz_6d tzd_6d
22 of 59 may 25, 2004 idt 79rc32438 figure 6 ddr sdram ac timing waveform - sdram read access rowa col a0 col a2 rowb nop actv nop rd rd nop nop prechg nop actv nop bnkx bnkx bnkx bnkx bnkx d0 d1 d2 d3 d0 d1 d2 d3 d0 d1 d2 d3 tdo_7m tdo_7m tdo_7m tdo_7m tskew_7g tskew_7g ddrckpx ddrcknx ddrcsnx ddraddr[13:0] ddrcmd 1 ddrcke ddrba[1:0] ddrdm[7:0] ddroen[3:0] ddrdqsx (ideal) ddrdata[31:0] 2 (ideal) ddrdqsx (min) ddrdata[31:0] 2 ddrdqsx (max) ddrdata[31:0] 2 1 ddrcmd contains ddrrasn, ddrcasn and ddrwen. 2 ddrdata is either 32-bits or 16-bits wide dependi ng on the dbw control bit in ddrc register (see chapter 7, ddr controller, in the rc32438 user reference manual). tac (min) tac (max)
23 of 59 may 25, 2004 idt 79rc32438 figure 7 ddr sdram timing waveform ? write access signal symbol reference edge 200mhz 233mhz 266mhz 300mhz unit conditions timing diagram reference min max min max min max min max memory and peripheral bus 1 see figures 8 and 9. maddr[21:0] tdo_8a extclk rising 0.0 5.0 0.0 5.0 0.0 5.0 0.0 5.0 ns tdz_8a 2 0.0 0.1 0.0 0.1 0.0 0.1 0.0 0.1 ns tzd_8a 2 0.5 2.3 0.5 2.3 0.5 2.3 0.5 2.3 ns maddr[25:22] tdo_8b extclk rising 0.0 6.5 0.0 6.5 0.0 6.5 0.0 6.5 ns tdz_8b 2 0.7 1.5 0.7 1.5 0.7 1.5 0.7 1.5 ns tzd_8b 2 1.2 3.3 1.2 3.3 1.2 3.3 1.2 3.3 ns table 8 memory and peripheral bus ac timing characteristics (part 1 of 3) 2 ddrdata is either 32-bits or 16-bits wide depending on the dbw control bit in ddrc register rowa col a0 col a2 nop actv nop wr wr nop nop nop nop nop bnkx bnkx ff dm0 dm1 dm3 ff d0 d1 d2 d3 tdo_7k tdo_7k tdo_7l tdo_7l tdo_7m tdo_7m tdo_7m tdo_7m tdo_7m ddrckpx ddrcknx ddrcsnx ddraddr[13:0] ddrcmd 1 ddrcke ddrba[1:0] ddroen[3:0] ddrdm[7:0] ddrdqsx ddrdata[31:0] 2 dm2 1 ddrcmd contains ddrrasn, ddrcasn and ddrwen. (see chapter 7, ddr controller, in the rc32438 user reference manual ). ddrdqsx
24 of 59 may 25, 2004 idt 79rc32438 mdata[15:0] tsu_8c extclk rising 7.0 ? 7.0 ? 7.0 ? 7.0 ? ns see figures 8 and 9 (cont.) thld_8c 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns tdo_8c 0.0 4.0 0.0 4.0 0.0 4.0 0.0 4.0 ns tdz_8c 2 0.0 0.1 0.0 0.1 0.0 0.1 0.0 0.1 ns tzd_8c 2 0.5 2.2 0.5 2.2 0.5 2.2 0.5 2.2 ns extclk 3 tper_8d none 10.0 ? 8.33 ? 7.5 ? 6.66 ? ns bdirn tdo_8e extclk rising 1.0 4.0 1.0 4.0 1.0 4.0 1.0 4.0 ns tdz_8e 2 -1.0 -0.1 -1.0 -0.1 -1.0 -0.1 -1.0 -0.1 ns tzd_8e 2 0.4 1.0 0.4 1.0 0.4 1.0 0.4 1.0 ns boen tdo_8f extclk rising 1.0 4.0 1.0 4.0 1.0 4.0 1.0 4.0 ns tdz_8f 2 0.1 0.4 0.1 0.4 0.1 0.4 0.1 0.4 ns tzd_8f 2 1.1 2.0 1.1 2.0 1.1 2.0 1.1 2.0 ns brn tsu_8g extclk rising 5.5 ? 5.5 ? 5.5 ? 5.5 ? ns thld_8g 0.0?0.0?0.0?0.0? ns bgn tdo_8h extclk rising 1.0 4.0 1.0 4.0 1.0 4.0 1.0 4.0 ns waitackn 4 tsu_8h extclk rising 5.8 ? 5.8 ? 5.8 ? 5.8 ? ns thld_8h 0.0?0.0?0.0?0.0? ns tpw_8h 2 none 2(ext- clk) ? 2(ext- clk) ? 2(ext- clk) ? 2(ext- clk) ?ns csn[5:0] tdo_8i extclk rising 0.0 4.0 0.0 4.0 0.0 4.0 0.0 4.0 ns tdz_8i 2 0.1 0.4 0.1 0.4 0.1 0.4 0.1 0.4 ns tzd_8i 2 0.6 2.2 0.6 2.2 0.6 2.2 0.6 2.2 ns rwn tdo_8j extclk rising 0.0 4.0 0.0 4.0 0.0 4.0 0.0 4.0 ns tdz_8j 2 -0.7 0.1 -0.7 0.1 -0.7 0.1 -0.7 0.1 ns tzd_8j 2 0.6 1.1 0.6 1.1 0.6 1.1 0.6 1.1 ns oen tdo_8k extclk rising 0.0 4.0 0.0 4.0 0.0 4.0 0.0 4.0 ns tdz_8k 2 -0.4 0.2 -0.4 0.2 -0.4 0.2 -0.4 0.2 ns tzd_8k 2 0.8 1.5 0.8 1.5 0.8 1.5 0.8 1.5 ns bwen[1:0] tdo_8l extclk rising 0.0 4.0 0.0 4.0 0.0 4.0 0.0 4.0 ns tdz_8l 2 0 0.2 0 0.2 0 0.2 0 0.2 ns tzd_8l 2 0.8 1.7 0.8 1.7 0.8 1.7 0.8 1.7 ns signal symbol reference edge 200mhz 233mhz 266mhz 300mhz unit conditions timing diagram reference min max min max min max min max table 8 memory and peripheral bus ac timing characteristics (part 2 of 3)
25 of 59 may 25, 2004 idt 79rc32438 figure 8 memory and peripheral bus ac timing waveform ? read access dmareqn[1:0] tpw_8n 2 none 2(iclk) ? 2(iclk) 2(iclk) ? 2(iclk) ? ns see figures 10 and 11. dmadonen[1:0] tsu_8o extclk rising 6.0 ? 6.0 ? 6.0 ? 6.0 ? ns thld_8o 1.0?1.0?1.0?1.0? ns dmafinn[1:0] tdo_8p extclk rising 1.5 6.0 1.5 6.0 1.5 6.0 1.5 6.0 ns cpu, inst tdo_8m extclk rising 2.0 10.0 2.0 10.0 2.0 10.0 2.0 10.0 ns see figures 8 and 9. 1. the rc32438 provides bus turnaround cycles to prevent bus contenti on when going from a read to write, write to read, and during external bus ownership. for example, there are no cycles where an external device and the rc3243 8 are both driving. see chapter 6, devi ce controller, in the rc32438 user refe rence manual. 2. the values for this symbol were determined by calculation, not by testing. 3. the frequency of extclk is programmable. see the external clock divider descr iption in table 3 of this data sheet. 4. waitackn must meet the setup and hold times if it is synchronous or the minimum pulse width if it is asynchronous. signal symbol reference edge 200mhz 233mhz 266mhz 300mhz unit conditions timing diagram reference min max min max min max min max table 8 memory and peripheral bus ac timing characteristics (part 3 of 3) addr[21:0] addr[25:22] 1111 data tdo_8f tdo_8f tdo_8e tdo_8e tzd_8c tdz_8c tdo_8k tdo_8k tdo_8i tdo_8i tdo_8b tdo_8a thld_8c tsu_8c extclk maddr[21:0] maddr[25:22] rwn csn[5:0] bwen[1:0] oen mdata[15:0] bdirn boen waitackn rc32438 samples read data tper_8d thigh_8d tlow_8d tdo_8m tdo_8m cpu, inst
26 of 59 may 25, 2004 idt 79rc32438 figure 9 memory and peripheral bus ac timing waveform ? write access figure 10 dmadonen and dmafinn ac timing waveform addr[21:0] addr[25:22] 1111 byte enables 1111 data tdo_8f tdo_8c tdo_8l tdo_8i tdo_8j tdo_8b tdo_8a extclk maddr[21:0] maddr[25:22] rwn csn[5:0] bwen[1:0] oen mdata[15:0] bdirn boen waitackn cpu, inst tdo_8m tdo_8p tdo_8p thld_8o tsu_8o data extclk dmadonenx mdata[15:0] maddr[25:0] dmafinnx address
27 of 59 may 25, 2004 idt 79rc32438 figure 11 dmareqn ac timing waveform signal symbol reference edge 200mhz 233mhz 266mhz 300mhz unit conditions timing diagram reference min max min max min max min max ethernet 1 1. there are two mii interfaces and the timing is the same for each. ?x? represents interface 0 or 1. miimdc tper_9a none 40.0 ? 33.3 ? 30.0 ? 30.0 ? ns see figure 12. thigh_9a, tlow_9a 16.0 ? 13.0 ? 12.0 ? 12.0 ? ns miimdio tsu_9b miimdc rising 10.0 ? 10.0 ? 10.0 ? 10.0 ? ns thld_9b 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns tdo_9b 2 2. the values for this symbol were determ ined by calculation, not by testing. 10 300 10 300 10 300 10 300 ns miixrxclk, miixtxclk 3 tper_9c none 399.96 400.4 399.96 400.4 399.96 400.4 399.96 400.4 ns 10 mbps thigh_9c, tlow_9c 140 260 140 260 140 260 140 260 ns trise_9c, tfall_9c ? 3.0 ? 3.0 ? 3.0 ? 3.0 ns miixrxclk, miixtxclk 3 tper_9d none 39.9 40.0 39.9 40.0 39.9 40.0 39.9 40.0 ns 100 mbps thigh_9d, tlow_9d 14.0 26.0 14.0 26.0 14.0 26.0 14.0 26.0 ns trise_9d, tfall_9d ? 2.0 ? 2.0 ? 2.0 ? 2.0 ns miixrxd[3:0], miixrxdv, miixrxer tsu_9e miixrxclk rising 10.0 ? 10.0 ? 10.0 ? 10.0 ? ns thld_9e 10.0 ? 10.0 ? 10.0 ? 10.0 ? ns miixtxd[3:0], miixtxenp, miixtxer tdo_9f miixtxclk rising 0.0 25.0 0.0 25.0 0.0 25.0 0.0 25.0 ns table 9 ethernet ac timing characteristics tpw_8n tpw_8n tpw_8n is the minimum amount of time before dmareqn is recognized as asserted or deasserted. extclk dmareqn iclk csn
28 of 59 may 25, 2004 idt 79rc32438 figure 12 ethernet ac timing waveform 3. the ethernet clock (miixrxclk and miixtxclk) frequency must be equal to or less than 1/2 iclk (miixrxclk and miixtxclk <= 1/2(i clk)). tdo_9b tdo_9b tdo_9f tdo_9f thld_9b tsu_9b tlow tlow_9a thigh_9a tper_9a tlow_9d tlow thigh_9d tper_9d thld_9e tsu_9e tlow_9d tlow thigh_9d tper_9d miixrxclk miixrxdv, miixrxd[3:0], miixrxer miixtxclk miixtxen, miixtxd[3:0], miixtxer miixmdc miixmdio (output) miixmdio (input)
29 of 59 may 25, 2004 idt 79rc32438 signal symbol reference edge 200mhz 233mhz 266mhz 300mhz unit conditions timing diagram reference min max min max min max min max pci 1 1. this pci interface conforms to the pci local bus specification, rev 2.2. pciclk 2 2. pciclk must be equal to or less than two times iclk (pciclk <= 2(iclk)) with a maximum pciclk of 66mhz. tper_10a none 15.0 30.0 15.0 30.0 15.0 30.0 15.0 30.0 ns 66 mhz pci see figure 13. thigh_10a, tlow_10a 6.0 ? 6.0 ? 6.0 ? 6.0 ? ns tslew_10a 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 v/ns pciad[31:0], pciben[3:0], pcidevseln, pciframen,pciir- dyn, pcilockn, pcipar, pci- perrn, pcis- topn, pcitrdy tsu_10b pciclk rising 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns thld_10b 0 ? 0 ? 0 ? 0 ? ns see figure 13 (cont.) tdo_10b 2.0 6.0 2.0 6.0 2.0 6.0 2.0 6.0 ns tdz_10b 3 3. the values for this symbol were determined by calculation, not by testing. ? 14.0 ? 14.0 ? 14.0 ? 14.0 ns tzd_10b 3 2.0 ? 2.0 ? 2.0 ? 2.0 ? ns pcigntn[3:0], pcireqn[3:0] tsu_10c pciclk rising 5.0 ? 5.0 ? 5.0 ? 5.0 ? ns thld_10c 0 ? 0 ? 0 ? 0 ? ns tdo_10c 2.0 6.0 2.0 6.0 2.0 6.0 2.0 6.0 ns pcirstn (output) 4 4. pcirstn is an output in host mode and an input in satellite mode. tpw_10d 3 none 4000 (clk) ? 4000 (clk) ? 4000 (clk) ? 4000 (clk) ? ns see figures 15 and 16 pcirstn (input) 4,5 5. to meet the pci delay specification from reset asserted to outputs floating, the pci reset should be logically combined with th e coldrstn input, instead of input on pcirstn. tpw_10e 3 none 2(clk) ? 2(clk) ? 2(clk) ? 2(clk) ? ns tdz_10e 3 pcirstn falling 6(clk) ? 6(clk) ? 6(clk) ? 6(clk) ? ns pciserrn 6 6. pciserrn and pcimuintn use open collector i/o types. tsu_10f pciclk rising 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns see figure 13 thld_10f 0 ? 0 ? 0 ? 0 ? ns tdo_10f 2.0 6.0 2.0 6.0 2.0 6.0 2.0 6.0 ns pcimuintn 6 tdo_10g pciclk rising 4.7 11.1 4.7 11.1 4.7 11.1 4.7 11.1 ns table 10 pci ac timing characteristics
30 of 59 may 25, 2004 idt 79rc32438 figure 13 pci ac timing waveform figure 14 pci ac timing wavefo rm ? pci reset in host mode figure 15 pci ac timing waveform ? pci reset in satellite mode tdo_10c tzd_10b tdz_10b tdo_10b thld_10c tsu_10c thld_10b tsu_10b thigh_10a tper_10a tper_10a valid valid pciclk bussed output point to point output bussed input point to point input tlow_10a tpw_10d tpw_10d pci interface enabled cold reset warm reset coldrstn pcirstn (output) rstn note: during and after cold reset, pcirstn is tri-stated and requires a pull-down to reach a low state. after the pci interface is enabled in host mode, pcirstn will be driven either high or low depending on the (tri-state) reset state of the 79rc32438. tdz_10e tpw_10e tpw_10e warm reset clkp pcirstn (input) rstn mdata[15:0] pci bus signals
31 of 59 may 25, 2004 idt 79rc32438 signal symbol reference edge 200mhz 233mhz 266mhz 300mhz unit conditions timing diagram reference min max min max min max min max i 2 c 1 1. for more information, see the i 2 c-bus specification by philips semiconductor. scl frequency none 0 100 0 100 0 100 0 100 khz 100 khz see figure 16. thigh_12a, tlow_12a 4.0?4.0?4.0?4.0? s trise_12a ? 1000 ? 1000 ? 1000 ? 1000 ns tfall_12a ? 300 ? 300 ? 300 ? 300 ns sda tsu_12b scl rising 250 ? 250 ? 250 ? 250 ? ns thld_12b 0 3.45 0 3.45 0 3.45 0 3.45 s trise_12b ? 1000 ? 1000 ? 1000 ? 1000 ns tfall_12b ? 300 ? 300 ? 300 ? 300 ns start or repeated start condition tsu_12c sda falling 4.7 ? 4.7 ? 4.7 ? 4.7 ? s thld_12c 4.0 ? 4.0 ? 4.0 ? 4.0 ? s stop condition tsu_12d sda rising 4.0 ? 4.0 ? 4.0 ? 4.0 ? s bus free time between a stop and start condi- tion tdelay_12e 4.7 ? 4.7 ? 4.7 ? 4.7 ? s scl frequency none 0 400 0 400 0 400 0 400 khz 400 khz thigh_12a, tlow_12a 0.6?0.6?0.6?0.6? s trise_12a ?300?300?300?300 ns tfall_12a ? 300 ? 300 ? 300 ? 300 ns sda tsu_12b scl rising 100 ? 100 ? 100 ? 100 ? ns thld_12b 00.900.900.900.9 s trise_12b ?300?300?300?300 ns tfall_12ba ? 300 ? 300 ? 300 ? 300 ns start or repeated start condition tsu_12c sda falling 0.6 ? 0.6 ? 0.6 ? 0.6 ? s thld_12c 0.6 ? 0.6 ? 0.6 ? 0.6 ? s stop condition tsu_12d sda rising 0.6 ? 0.6 ? 0.6 ? 0.6 ? s bus free time between a stop and start condi- tion tdelay_12e 1.3 ? 1.3 ? 1.3 ? 1.3 ? s table 11 i 2 c ac timing characteristics
32 of 59 may 25, 2004 idt 79rc32438 figure 16 i 2 c ac timing waveform figure 17 gpio ac timing waveform signal symbol reference edge 200mhz 233mhz 266mhz 300mhz unit conditions timing diagram reference minmaxminmaxminmaxminmax gpio gpio[31:0] 1 1. gpio signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. tpw_13b 2 2. the values for this symbol were determined by calculation, not by testing. none 2(iclk) ? 2(iclk) ? 2(iclk) ? 2(iclk) ? ns see figure 17. table 12 gpio ac timing characteristics tsu_12d thld_12c tsu_12c tsu_12b thld_12b thigh_12a thld_12c tlow_12a sda scl tdelay_12e tdo_13a tdo_13a tpw_13b tpw_13b thld_13a tsu_13a extclk gpio (synchronous output) gpio (synchronous input) gpio (asynchronous input)
33 of 59 may 25, 2004 idt 79rc32438 figure 18 spi ac timing waveform ? pci configurations load signal symbol reference edge 200mhz 233mhz 266mhz 300mhz unit conditions timing diagram reference min max min max min max min max spi 1 1. in spi mode, the sck period and sampling edge are programmable. in pci mode, the sck period is fixed and the sampling edge is r ising. sck tper_15a none ? 1920 ? 1920 ? 1920 ? 1920 ns 33 mhz pci see figures 18, 19, 20 and 21. tper_15a ? 960 ? 960 ? 960 ? 960 ns 66 mhz pci tper_15a 100 166667 100 166667 100 166667 100 166667 ns spi thigh_15a, tlow_15a 930 990 930 990 930 990 930 990 ns 33 mhz pci thigh_15a, tlow_15a 465 495 465 495 465 495 465 495 ns 66 mhz pci thigh_15a, tlow_15a 40 83353 40 83353 40 83353 40 83353 ns spi sdi tsu_15b sck rising or falling 60 ? 60 ? 60 ? 60 ? ns spi or pci thld_15b 60 ? 60 ? 60 ? 60 ? ns sdo tdo_15c sck rising or falling 060060060060 nsspi or pci pcieecs 2 2. pcieecs is the pci serial eeprom chip select. it is an alternate fu nction of pcigntn[1]. tdo_15d sck rising or falling 060060060060 nspci sck, sdi, sdo 3 3. in bit i/o mode, sck, sdi, and sdo must meet the setup and hold times if they are synchronous or the minimum pulse width if the y are asynchronous. tpw_15e none 2(iclk) ? 2(iclk) ? 2(iclk) ? 2(iclk) ? ns bit i/o table 13 spi ac timing characteristics tdo_15c tdo_15d thld_15b tsu_15b tlow_15a tlow_15a thigh_15a thigh_15a tper_15a msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb loading pci configuration regist ers through spi from an eeprom. msb bit 6 bit 4 bit 2 lsb bit 5 bit 3 bit 1 sck pcieecs sdi sdo
34 of 59 may 25, 2004 idt 79rc32438 figure 19 spi ac timing waveform ? clock polarity 0, clock phase 0 figure 20 spi ac timing waveform ? clock polarity 0, clock phase 1 figure 21 spi ac timing waveform ? bit i/o mode tdo_15c thld_15b tsu_15b tlow_15a thigh_15a tper_15a msb bit 6 bit 4 bit 5 bit 3 bit 2 bit 1 lsb control bits cpol = 0, cpha = 0 in the spi control register, spc. msb bit 6 bit 4 bit 2 lsb bit 5 bit 3 bit 1 sck sdi sdo tdo_15c thld_15b tsu_15b tlow_15a thigh_15a tper_15a msb bit 6 bit 4 bit 5 bit 3 bit 2 bit 1 lsb control bits cpol = 0, cpha = 1 in the spi control register, spc. msb bit 6 bit 4 bit 5 bit 3 bit 1 bit 2 lsb sck sdi sdo tdo_15e tdo_15e tpw_15e tpw_15e thld_15e tsu_15e extclk sck, sdi, sdo (output) sck, sdi, sdo (input) sck, sdi, sdo (asynchronous input)
35 of 59 may 25, 2004 idt 79rc32438 signal symbol reference edge 200mhz 233mhz 266mhz 300mhz unit conditions timing diagram reference min max min max min max min max ejtag and jtag jtag_tck tper_16a none 25.0 50.0 25.0 50.0 25.0 50.0 25.0 50.0 ns see figure 22. thigh_16a, tlow_16a 10.0 25.0 10.0 25.0 10.0 25.0 10.0 25.0 ns jtag_tms 1 , jtag_tdi 1. the jtag specification, ieee 1149. 1, recommends that both jtag_tms and ejtag_tms should be held at 1 while the signal applied a t jtag_trst_n changes from 0 to 1. otherwise, a race may occur if jtag_trst_n is deasserted (going fr om low to high) on a rising edge of jtag_tck when either jtag _tms or ejtag_tms is low, because the tap controller might go to either the run-test/idl e state or stay in the test-logic-reset state. tsu_16b jtag_tck rising 2.4 ? 2.4 ? 2.4 ? 2.4 ? ns thld_16b 1.0 ? 1.0 ? 1.0 ? 1.0 ? ns jtag_tdo tdo_16c jtag_tck falling ? 11.3 ? 11.3 ? 11.3 ? 11.3 ns tdz_16c 2 2. the values for this symbol were deter mined by calculation, not by testing. ? 11.3 ? 11.3 ? 11.3 ? 11.3 ns jtag_trst_n tpw_16d 2 none 25.0 ? 25.0 ? 25.0 ? 25.0 ? ns ejtag_tms 1 tsu_16e jtag_tck rising 2.0 ? 2.0 ? 2.0 ? 2.0 ? ns thld_6e 1.0 ? 1.0 ? 1.0 ? 1.0 ? ns vsense trise_16f none ? 2 ? 2 ? 2 ? 2 sec measured from 0.5v (t active ) see figure 24. table 14 jtag ac timing characteristics
36 of 59 may 25, 2004 idt 79rc32438 figure 22 jtag ac timing waveform the ieee 1149.1 specification requires that the jtag and ejtag tap controllers be reset at power-up whether or not the interfac es are used for a boundary scan or a probe. reset can occur through a pull-down resi stor on jtag_trst_n if the probe is not connected. however, on-chip pull-up resistors are implemented on the rc32438 due to an ieee 1149.1 requirement. having on-chip pull-up and external pull-down resis tors for the jtag_trst_n signal requires special care in the design to ensure t hat a valid logical level is provided to jtag_trst_n, such as using a small external pull-down resistor to ensure this level overrides the on-chip pull-up. an alte rnative is to use an active power-up res et circuit for jtag_trst_n, which drives jtag_trst_n low only at power-up and then holds jtag_trst_n high afterwards with a pull-up resistor. figure 23 shows the electrical connection of the ejtag probe target system connector. figure 23 target system electrical ejtag connection tpw_16d tpw_16d tdz_16c tdo_16c thld_16e tsu_16e thld_16b tsu_16b thld_16b tsu_16b tlow_16a tlow_16a tper_16a thigh_16a jtag_tck jtag_tdi jtag_tms ejtag_tms jtag_tdo jtag_trst_n gnd 1 gnd gnd gnd gnd trst* tdi tdo tms tck rst* dint jtag_trst_n jtag_tdi jtag_tdo ejtag_tms jtag_tck gnd vdd gnd vccio voltage reference pull-up pull-down series-res. coldrstn target system reset circuit pull-up other reset sources rc32438 no connect or rstn vsense
37 of 59 may 25, 2004 idt 79rc32438 using the ejtag probe in figure 23, the pull-up resistors for jtag_tdo and rst*, the pull- down resistor for jtag_trst_n, and the series resistor for jtag_tdo must be adjusted to the specific design. however, the recommended pull-up/down resistor is 1.0 k ? because a low value reduces crosstalk on the cable to the connector, allowing higher jtag_tck frequencies. a typical value for the series resistor is 33 ? . recommended resistor values have 5% toler- ance. if a probe is used, the pull-up resistor on jtag_tdo must ensur e that the jtag_tdo level is high when no probe is connected and the jtag_tdo output is tri-stated. this require ment allows reliable connection of the prob e if it is hooked-up when the power is al ready on (hot plug). the pull-up resistor value of around 47 k ? should be sufficient. optional diodes to protect against overshoot and undershoot voltage can be added on the signals of the chip with ejtag. if a probe is used, the rst* signal must have a pull-up resistor because it is controlled by an open-collector (oc) driver in t he probe, and thus is actively pulled low only. the pull-up resist or is responsible for the high value w hen not driven by the probe of 25pf. the inpu t on the target system reset circuit must be able to accept the rise time when the pull- up resistor charges the capacitance to a high logical level. v cc i/o must connect to a voltage reference that drops rapidly to below 0.5v when the tar get system loses power, even with a capacitive load of 25pf. the probe can thus detect the lost power condition. for additional information on ejtag, refer to chapter 20 of the rc32438 user reference manual. voltage sense signal timing figure 24 voltage sense signal timing the target system must ensure that t rise is obeyed after the system reaches 0.5v (t active ), so the probe can use this value to determine when the target has powered-up. the probe is allowed to measure the t rise time from a higher value than t active (but lower than vcc i/o minimum) because the stable indication in this case comes later than the time when ta rget power is guaranteed to be stable. if jtag_trst_n is assert ed by a pulse at power-up, this reset must be completed after t rise . if jtag_trst_n is asserted by a pull-down re sistor, the probe will control jtag_trst_n. at power-down, no power is indicated to the probe when vcc i/o drops under the t active value, which the probe uses to stop driving the input signals, except for the probe rst*. phase-locked loop (pll) the phase-locked loop (pll) multiplies the ex ternal oscillator input (pin clk) accord ing to the parameter provided by the boot configuration vector to create the processor clock (pclk). inherently, pll circui ts are only capable of generating clock frequencies within a limite d range. pll filters it is recommended that the system designer pr ovide a filter network of passive com ponents for the pll analog and digital power supplies. the pll circuit power and pll circuit ground s hould be isolated from power and ground with a filter circuit such as the one shown i n figure 25. because the optimum values for the filter components depend upon the application and the system noise environment, these values should be considered as starting points for further exper imentation within your specific application. vsense t rise_16f t active
38 of 59 may 25, 2004 idt 79rc32438 figure 25 pll filter circuit for noisy environments recommended operating supply voltages recommended operating temperatures capacitive load deration refer to the 79rc32438 ibis mo del on the idt web site (www.idt.com). symbol parameter clock speed minimum typical maximum unit v ss common ground all speeds 0 0 0 v v ss pll pll ground v cc i/o i/o supply except for sstl_2 1 1. sstl_2 i/os are used to connect to ddr sdram. 3.0 3.3 3.6 v v cc si/o i/o supply for sstl_2 1 2.3 2.5 2.7 v v cc pll pll supply 200mhz, 233mhz 1.1 1.2 1.3 v 266mhz, 300mhz 1.2 1.3 1.4 v v cc core internal logic supply 200mhz, 233mhz 1.1 1.2 1.3 v 266mhz, 300mhz 1.2 1.3 1.4 v ddrvref 2 2. peak-to-peak ac noise on ddrvref may not exceed 2% ddrvref (dc). sstl_2 input reference voltage all speeds 0.5(vccsi/o) 0.5(vccsi/o) 0.5(vccsi/o) v v tt 3 3. v tt of the sstl_2 transmitting device must track ddrvref of the receiving device. sstl_2 termination voltage ddrvref - 0.04 ddrvref ddrvref + 0.04 v table 15 rc32438 operating voltages grade temperature commercial 0 c to +70 c ambient industrial -40 c to +85 c ambient table 16 rc32438 operating temperatures 10 f 0.1 f 100 pf v cc v ss v cc pll v ss pll 10 ohm 1 rc32438 v cc pll v ss pll
39 of 59 may 25, 2004 idt 79rc32438 power-on sequence three power-on sequences are given below. sequ ence #1 is recommended because it will prev ent i/o conflicts and will also allow the input signals to propagate when the i/o powers are brought up. note: the esd diodes may be damaged if one of the voltages is appl ied and one of the other voltages is at a ground level. a. recommended sequence t2 > 0 whenever possible (v cc core) t1 - t2 can be 0 (v cc si/o followed by v cc i/o) b. reverse voltage sequence if sequence a is not feasible, then sequence b can be used: t1 <50ms and t2 <50ms to prevent damage. c. simultaneous power-up vcci/o, vccsi/o, and vcccore can be powered up simultaneously. 1.2v 3.3v 2.5v time t1 t2 v cc i/o v cc si/o v cc core vcci/o -- 3.3v vccsi/o -- 2.5v vcccore (266/300mhz) -- 1.3v vcccore (200/233mhz) -- 1.2v vcc1.2 vcc3.3 vcc2.5 time t1 t2 vcci/o -- 3.3v vccsi/o -- 2.5v vcccore (266/300mhz) -- 1.3v vcccore (200/233mhz) -- 1.2v vcccore vccsi/o vcci/o
40 of 59 may 25, 2004 idt 79rc32438 power consumption dc electrical characteristics values based on systems running at recommended su pply voltages, as shown in table 15. note: see table 2, pin characteristic s, for a complete i/o listing. parameter 200mhz 233mhz 266mhz 300mhz unit conditions typ. max. typ. max. typ. max. typ. max. i cc i/o 130 150 180 200 220 250 260 300 ma c l = 35 pf t ambient = 25 o c max. values use the maximum volt- ages listed in table 15. typical values use the typical voltages listed in that table. i cc si/o 100 120 150 170 200 220 250 270 ma i cc core, i cc pll normal mode 460 500 510 550 610 650 680 730 ma power dissipation normal mode 1.2 1.6 1.6 1.9 2.0 2.4 2.4 2.7 w table 17 rc32438 power consumption i/o type para- meter min. typical max. unit conditions low drive output i ol ?14.0?ma v ol = 0.4v i oh ? -12.0 ? ma v oh = 1.5v high drive output i ol ?24.0?ma v ol = 0.4v i oh ? -42.0 ? ma v oh = 1.5v schmitt trigger input (sti) v il -0.3 ? 0.8 v ? v ih 2.0 ? v cc i/o + 0.5 v? sstl_2 (for ddr sdram) i ol 7.6 ? ? ma v ol = 0.5v i oh -7.6 ? ? ma v oh = 1.76v v il -0.3 ? 0.5(v cc si/o) - 0.18 v v ih 0.5(v cc si/o) + 0.18 ? v cc si/o + 0.3 v table 18 dc electrical characteristics (part 1 of 2)
41 of 59 may 25, 2004 idt 79rc32438 ac test conditions figure 26 ac test conditions pci i oh (ac) switching -12(v cc i/o) ? ?ma0 < v out < 0.3(v cc i/o) -17.1(v cc i/o - v out ) ? ?ma0.3(v cc i/o) < v out < 0.9(v cc i/o) ?? -32(v cc i/o) ? 0.7(v cc i/o) i ol (ac) switch- ing +16(v cc i/o) ? ma v cc i/o > v out > 0.6(v cc i/o) +26.7(v out ) ? ma 0.6(v cc i/o) > v out > 0.1(v cc i/o) ? ? +38(v cc i/o) ma v out = 0.18(v cc i/o) v il -0.3 ? 0.3(v cc i/o) v v ih 0.5(v cc i/o) ? 5.5 v capacitance c in ? ? 8.0 pf ? leakage inputs ??+ 10 avcc (max) i/o leak w / o pull-ups/downs ??+ 10 avcc (max) i/o leak with pull-ups/downs ??+ 80 avcc (max) i/o type para- meter min. typical max. unit conditions table 18 dc electrical characteristics (part 2 of 2) input reference voltage parameter value units sstl i/o other i/o input pulse levels 0 to 2.5 0 to 3.3 v input rise/fall 0.8 1.0 ns input reference level 0.5(vccsi/o) 0.5(vcci/o) v output reference levels 1.25 1.5 v ac test load 35 35 pf rc32438 output . 50 ? 50 ? test point
42 of 59 may 25, 2004 idt 79rc32438 absolute maximum ratings symbol parameter min 1 1. functional and tested operating conditions are given in table 15. absolute maximum ratings are stress ratings only, and func- tional operation at the maxi mums is not guaranteed. stresses beyond those listed may affect device reliability or cause perma- nent damage to the device. max 1 unit v cc i/o i/o supply except for sstl_2 2 2. sstl_2 i/os are used to connect to ddr sdram. -0.6 4.0 v v cc si/o i/o supply for sstl_2 2 -0.6 3.0 v v cc core core supply voltage -0.6 2.0 v v cc pll pll supply -0.6 2.0 v vini/o i/o input voltage except for sstl_2 -0.6 v cc i/o+ 0.5 v vinsi/o i/o input voltage for sstl_2 -0.6 v cc si/o+ 0.5 v t a industrial ambient operating temperature -40 +85 c t a commercial ambient operating temperature 0 +70 c t s storage temperature -40 +125 c table 19 absolute maximum ratings
43 of 59 may 25, 2004 idt 79rc32438 package pin-out ? 416-pbga signal pinout for rc32438 the following table lists the pin numbers, signal names, and number of alternate f unctions for the rc32438 device. signal names ending with an ?_n? or ?n? are active when low. pin function alt pin function alt pin function alt pin function alt a1 mii0cl d11 v ss p1 gpio[00] 1 ac17 v ss a2 gpio[25] 1 d12 v ss p2 miimdio ac18 v ss a3 gpio[31] d13 v cc core p3 gpio[02] 1 ac19 v ss a4 csn[05] d14 v cc core p4 v cc i/o ac20 v cc i/o a5 csn[02] d15 v cc core p23 v cc core ac21 v cc i/o a6 bwen[01] d16 v ss p24 ddrdm[03] ac22 v cc i/o a7 boen d17 v ss p25 ddrdata[31] ac23 vcc si/o a8 mdata[15] d18 v ss p26 ddrdata[30] ac24 vcc si/o a9 mdata[14] d19 v ss r1 inst ac25 ddroen[00] a10 mdata[10] d20 v cc i/o r2 ejtag_tms ac26 ddraddr[00] a11 mdata[07] d21 vcc si/o r3 v ss ad1 jtag_trst_n a12 mdata[06] d22 vcc si/o r4 v cc i/o ad2 jtag_tms a13 gpio[29] d23 vcc si/o r23 vcc si/o ad3 gpio[15] 1 a14 gpio[22] 1 d24 vcc si /o r24 ddrdata[29] ad4 sda a15 maddr[21] d25 ddrdata[11] r25 ddraddr[13] ad5 gpio[27] 1 a16 maddr[19] d26 ddrdata[10] r26 ddrcsn[01] ad6 pciad[30] a17 maddr[16] e1 mii0txd[02] t1 nc ad7 pciad[26] a18 maddr[13] e2 mii0txd[00] t2 gpio[03] 1 ad8 pcicben[03] a19 maddr[10] e3 mii0txd[ 01] t3 cpu ad9 pciad[21] a20 maddr[07] e4 v ss t4 v cc i/o ad10 pciad[18] a21 maddr[05] e23 vcc si/o t23 vcc si/o ad11 pcireqn[01] a22 maddr[02] e24 ddrdata[09] t24 ddrcsn[00] ad12 pciclk a23 rstn e25 ddrdata[12] t25 ddraddr[10] ad13 pcigntn[00] a24 ddrdata[02] e26 ddrdm[01] t26 ddraddr[12] ad14 pciirdyn a25 ddrdata[04] f1 mii0txer u1 jtag_tdi ad15 pcistopn a26 ddrdata[05] f2 mii0txd[03] u2 jtag_tck ad16 pciperrn b1 mii0crs f3 mii0txenp u3 jtag_tdo ad17 pciad[15] b2 waitackn f4 v ss u4 v cc i/o ad18 pciad[11] b3 rwn f23 vcc si/o u23 v ss ad19 pciad[08] b4 csn[04] f24 ddrdqs[01] u24 ddraddr[11] ad20 pciad[06] b5 csn[01] f25 ddrdata[15] u25 ddrwen ad21 pcigntn[03] b6 bwen[00] f26 ddrdata[14] u26 ddraddr[09] ad22 pciad[00] b7 bgn g1 mii0rxer v1 sdo ad23 pciad[04] b8 mdata[13] g2 mii0rxdv v2 sdi ad24 ddrdm[05] table 20 rc32438 416-pin signal pin-out (part 1 of 3)
44 of 59 may 25, 2004 idt 79rc32438 b9 mdata[11] g3 mii0txclk v3 gpio[05] 1 ad25 ddroen[02] b10 mdata[03] g4 v ss v4 v ss ad26 ddroen[01] b11 mdata[08] g23 v ss v23 v ss ae1 n/c b12 mdata[02] g24 ddrckp[00] v24 ddraddr[08] ae2 gpio[13] 1 b13 gpio[23] 1 g25 ddrdata[16] v25 ddrrasn ae3 gpio[18] 1 b14 maddr[20] g26 ddrdata[13] v26 ddrcasn ae4 gpio[24] 1 b15 gpio[20] 1 h1 mii1crs w1 gpio[04] 1 ae5 gpio[26] 1 b16 maddr[17] h2 mii1cl w2 sck ae6 pciad[31] b17 maddr[14] h3 mii1rxclk w3 clk ae7 pciad[28] b18 maddr[12] h4 v ss w4 v ss ae8 pciad[25] b19 maddr[09] h23 v ss w23 v ss ae9 gpio[30] 1 b20 maddr[06] h24 ddrckn[00] w24 ddraddr[07] ae10 pciad[22] b21 maddr[03] h25 ddrdata[18] w25 ddraddr[06] ae11 pciad[19] b22 maddr[00] h26 ddrvref w26 ddrba[01] ae12 pciad[16] b23 ddrdata[01] j1 mii1rxd[01] y1 gpio[06] 1 ae13 pcirstn b24 ddrdqs[00] j2 mii1rxd[00] y2 v cc pll ae14 pcireqn[02] b25 ddrdm[00] j3 mii1rxd[03] y3 gpio[08] 1 ae15 pciframen b26 ddrdata[06] j4 v ss y4 v ss ae16 pcidevseln c1 mii0rxd[00] j23 v ss y23 v ss ae17 pcilockn c2 mii0rxclk j24 ddrdata[17] y24 ddrckn[01] ae18 pcicben[01] c3 extclk j25 ddrdata[21] y25 ddrba[00] ae19 pciad[13] c4 coldrstn j26 ddrdata[19] y26 ddraddr[05] ae20 pciad[10] c5 oen k1 mii1rxdv aa1 v ss pll ae21 pcicben[00] c6 csn[03] k2 mii1rxd[02] aa2 gpio[07] 1 ae22 pciad[05] c7 csn[00] k3 mii1txclk aa3 v cc pll ae23 pciad[02] c8 brn k4 v cc core aa4 v ss ae24 pcigntn[01] c9 bdirn k23 v ss aa23 v ss ae25 ddrdm[07] c10 mdata[12] k24 ddrdata[20] aa24 ddrckp[01] ae26 ddrdm[04] c11 mdata[09] k25 ddrdqs[02] aa25 ddraddr[03] af1 gpio[16] 1 c12 mdata[01] k26 ddrcke aa26 ddraddr[04] af2 gpio[17] 1 c13 mdata[05] l1 mii1txd[00] ab1 gpio[09] 1 af3 gpio[19] 1 c14 mdata[04] l2 mii1rxer ab2 gpio[14] 1 af4 scl c15 mdata[00] l3 mii1txd[03] ab3 gpio[11] 1 af5 gpio[28] 1 c16 gpio[21] 1 l4 v cc core ab4 v ss af6 pciad[29] c17 maddr[18] l23 v cc core ab23 v ss af7 pciad[27] c18 maddr[15] l24 ddrdm[02] ab24 v cc si/o af8 pciad[24] c19 maddr[11] l25 ddrdata[24] ab25 ddraddr[01] af9 pciad[23] pin function alt pin function alt pin function alt pin function alt table 20 rc32438 416-pin signal pin-out (part 2 of 3)
45 of 59 may 25, 2004 idt 79rc32438 rc32438 power pins c20 maddr[08] l26 ddrdata[22] ab26 ddraddr[02] af10 pciad[20] c21 maddr[04] m1 mii1txd[02] ac1 v ss pll af11 pciad[17] c22 maddr[01] m2 mii1txd[01] a c2 gpio[10] 1 af12 pcireqn[03] c23 ddrdata[00] m3 miimdc ac3 gpio[12] 1 af13 pcireqn[00] c24 ddrdata[03] m4 v cc core ac4 v ss af14 pcicben[02] c25 ddrdata[08] m23 v cc core ac5 v ss af15 pcitrdyn c26 ddrdata[07] m24 ddrdata[23] ac6 v ss af16 pciserrn d1 mii0rxd[03] m25 ddrdata[27] ac7 v cc i/o af17 pcipar d2 mii0rxd[01] m26 ddrdata[25] ac8 v cc i/o af18 pciad[14] d3 mii0rxd[02] n1 mii1txer ac9 v cc i/o af19 pciad[12] d4 v ss n2 mii1txenp ac10 v ss af20 pciad[09] d5 v ss n3 gpio[01] 1 ac11 v ss af21 pciad[07] d6 v ss n4 v cc core ac12 v ss af22 pciad[03] d7 v cc i/o n23 v cc core ac13 v cc core af23 pciad[01] d8 v cc i/o n24 ddrdata[26] ac14 v cc core af24 pcigntn[02] d9 v cc i/o n25 ddrdata[28] ac15 v cc core af25 ddrdm[06] d10 v ss n26 ddrdqs[03] ac16 v ss af26 ddroen[03] v cc i/o v cc si/o v cc core v cc pll d7 d21 d13 y2, aa3 d8 d22 d14 d9 d23 d15 d20 d24 k4 p4 e23 l4 r4 f23 l23 t4 r23 m4 u4 t23 m23 ac7 ab24 n4 ac8 ac23 n23 ac9 ac24 p23 ac20 ac13 ac21 ac14 ac22 ac15 table 21 rc32438 power pins pin function alt pin function alt pin function alt pin function alt table 20 rc32438 416-pin signal pin-out (part 3 of 3)
46 of 59 may 25, 2004 idt 79rc32438 rc32438 ground pins v ss v ss v ss v ss v ss pll d4 l10 p13 u15 aa1, ac1 d5 l11 p14 u16 d6 l12 p15 u17 d10 l13 p16 u23 d11 l14 p17 v4 d12 l15 r3 v23 d16 l16 r10 w4 d17 l17 r11 w23 d18 m10 r12 y4 d19 m11 r13 y23 e4 m12 r14 aa4 f4 m13 r15 aa23 g4 m14 r16 ab4 g23 m15 r17 ab23 h4 m16 t10 ac4 h23 m17 t11 ac5 j4 n10 t12 ac6 j23 n11 t13 ac10 k10 n12 t14 ac11 k11 n13 t15 ac12 k12 n14 t16 ac16 k13 n15 t17 ac17 k14 n16 u10 ac18 k15 n17 u11 ac19 k16 p10 u12 k17 p11 u13 k23 p12 u14 table 22 rc32438 ground pins
47 of 59 may 25, 2004 idt 79rc32438 rc32438 alternate signal functions rc32438 signals listed alphabetically the following table lists the rc32438 pins in alphabetical order. pin gpio alternate pin gpio alternate pin gpio alternate a14 gpio[22] maddr[24] y1 gpio[06] u0rtsn ae2 gpio[13] u1ctsn b13 gpio[23] maddr[25] y3 gpio[08] u1sout ae3 gpio[18] dmafinn[0] b15 gpio[20] maddr[22] aa2 gpio[07] u0ctsn ae4 gpio[24] pcireqn[4] c16 gpio[21] maddr[23] ab1 gpio[09] u1sinp ae5 gpio[26] pcigntn[4] n3 gpio[01] u0sinp ab2 gpio[14] dmareqn[0] ae9 gpio[30] pcimuintn p1 gpio[00] u0sout ab3 gpio[11] u1dsrn af1 gpio[16] dmadone[0] p3 gpio[02] u0rin ac2 gpio[10] u1dtrn af2 gpio[17] dmadone[1] t2 gpio[03] u0dcdn ac3 gpio[12] u1rtsn af3 gpio[19] dmafinn[1] v3 gpio[05] u0dsrn ad3 gpio[15] dmareqn[1] af5 gpio[28] pcigntn[5] w1 gpio[04] u0dtrn ad5 gpio[27] pcireqn[5] table 23 rc32438 alternate signal functions signal name i/o type location signal category bdirn o c9 memory and peripheral bus bgn o b7 memory and peripheral bus boen o a7 memory and peripheral bus brn i c8 memory and peripheral bus bwen[00] o b6 memory and peripheral bus bwen[01] o a6 memory and peripheral bus clk i w3 system coldrstn i c4 system cpu o t3 debug csn[00] o c7 memory and peripheral bus csn[01] o b5 csn[02] o a5 csn[03] o c6 csn[04] o b4 csn[05] o a4 table 24 rc32438 alphabetical signal list (part 1 of 9)
48 of 59 may 25, 2004 idt 79rc32438 ddraddr[00] o ac26 ddr bus ddraddr[01] o ab25 ddraddr[02] o ab26 ddraddr[03] o aa25 ddraddr[04] o aa26 ddraddr[05] o y26 ddraddr[06] o w25 ddraddr[07] o w24 ddraddr[08] o v24 ddraddr[09] o u26 ddraddr[10] o t25 ddraddr[11] o u24 ddraddr[12] o t26 ddraddr[13] o r25 ddrba[00] o y25 ddrba[01] o w26 ddrcasn o v26 ddrcke o k26 ddrckn[00] o h24 ddrckn[01] o y24 ddrckp[00] o g24 ddrckp[01] o aa24 ddrcsn[00] o t24 ddrcsn[01] o r26 ddrdata[00] i/o c23 ddrdata[01] i/o b23 ddrdata[02] i/o a24 ddrdata[03] i/o c24 ddrdata[04] i/o a25 ddrdata[05] i/o a26 ddrdata[06] i/o b26 ddrdata[07] i/o c26 ddrdata[08] i/o c25 ddrdata[09] i/o e24 ddrdata[10] i/o d26 signal name i/o type location signal category table 24 rc32438 alphabetical signal list (part 2 of 9)
49 of 59 may 25, 2004 idt 79rc32438 ddrdata[11] i/o d25 ddr bus ddrdata[12] i/o e25 ddrdata[13] i/o g26 ddrdata[14] i/o f26 ddrdata[15] i/o f25 ddrdata[16] i/o g25 ddrdata[17] i/o j24 ddrdata[18] i/o h25 ddrdata[19] i/o j26 ddrdata[20] i/o k24 ddrdata[21] i/o j25 ddrdata[22] i/o l26 ddrdata[23] i/o m24 ddrdata[24] i/o l25 ddrdata[25] i/o m26 ddrdata[26] i/o n24 ddrdata[27] i/o m25 ddrdata[28] i/o n25 ddrdata[29] i/o r24 ddrdata[30] i/o p26 ddrdata[31] i/o p25 ddrdm[00] o b25 ddrdm[01] o e26 ddrdm[02] o l24 ddrdm[03] o p24 ddrdm[04] o ae26 ddrdm[05] o ad24 ddrdm[06] o af25 ddrdm[07] o ae25 ddrdqs[00] i/o b24 ddrdqs[01] i/o f24 ddrdqs[02] i/o k25 ddrdqs[03] i/o n26 ddroen[00] o ac25 ddroen[01] o ad26 signal name i/o type location signal category table 24 rc32438 alphabetical signal list (part 3 of 9)
50 of 59 may 25, 2004 idt 79rc32438 ddroen[02] o ad25 ddr bus ddroen[03] o af26 ddrrasn o v25 ddrvref i h26 ddrwen o u25 ejtag_tms i r2 ejtag/ice extclk o c3 system gpio[00] i/o p1 general purpose input/output gpio[01] i/o n3 gpio[02] i/o p3 gpio[03] i/o t2 gpio[04] i/o w1 gpio[05] i/o v3 gpio[06] i/o y1 gpio[07] i/o aa2 gpio[08] i/o y3 gpio[09] i/o ab1 gpio[10] i/o ac2 gpio[11] i/o ab3 gpio[12] i/o ac3 gpio[13] i/o ae2 gpio[14] i/o ab2 gpio[15] i/o ad3 gpio[16] i/o af1 gpio[17] i/o af2 gpio[18] i/o ae3 gpio[19] i/o af3 gpio[20] i/o b15 gpio[21] i/o c16 gpio[22] i/o a14 gpio[23] i/o b13 gpio[24] i/o ae4 gpio[25] i/o a2 gpio[26] i/o ae5 gpio[27] i/o ad5 signal name i/o type location signal category table 24 rc32438 alphabetical signal list (part 4 of 9)
51 of 59 may 25, 2004 idt 79rc32438 gpio[28] i/o af5 general purpose input/output gpio[29] i/o a13 gpio[30] i/o ae9 gpio[31] i/o a3 inst o r1 debug jtag_tck i u2 ejtag/ice jtag_tdi i u1 jtag_tdo o u3 jtag_tms i ad2 jtag_trst_n i ad1 maddr[00] o b22 memory and peripheral bus maddr[01] o c22 maddr[02] o a22 maddr[03] o b21 maddr[04] o c21 maddr[05] o a21 maddr[06] o b20 maddr[07] o a20 maddr[08] o c20 maddr[09] o b19 maddr[10] o a19 maddr[11] o c19 maddr[12] o b18 maddr[13] o a18 maddr[14] o b17 maddr[15] o c18 maddr[16] o a17 maddr[17] o b16 maddr[18] o c17 maddr[19] o a16 maddr[20] o b14 maddr[21] o a15 mdata[00] i/o c15 mdata[01] i/o c12 signal name i/o type location signal category table 24 rc32438 alphabetical signal list (part 5 of 9)
52 of 59 may 25, 2004 idt 79rc32438 mdata[02] i/o b12 memory and peripheral bus mdata[03] i/o b10 mdata[04] i/o c14 mdata[05] i/o c13 mdata[06] i/o a12 mdata[07] i/o a11 mdata[08] i/o b11 mdata[09] i/o c11 mdata[10] i/o a10 mdata[11] i/o b9 mdata[12] i/o c10 mdata[13] i/o b8 mdata[14] i/o a9 mdata[15] i/o a8 mii0cl i a1 ethernet interfaces mii0crs i b1 mii0rxclk i c2 mii0rxd[00] i c1 mii0rxd[01] i d2 mii0rxd[02] i d3 mii0rxd[03] i d1 mii0rxdv i g2 mii0rxer i g1 mii0txclk i g3 mii0txd[00] o e2 mii0txd[01] o e3 mii0txd[02] o e1 mii0txd[03] o f2 mii0txenp o f3 mii0txer o f1 mii1cl i h2 mii1crs i h1 mii1rxclk i h3 mii1rxd[00] i j2 mii1rxd[01] i j1 signal name i/o type location signal category table 24 rc32438 alphabetical signal list (part 6 of 9)
53 of 59 may 25, 2004 idt 79rc32438 mii1rxd[02] i k2 ethernet interfaces mii1rxd[03] i j3 mii1rxdv i k1 mii1rxer i l2 mii1txclk i k3 mii1txd[00] o l1 mii1txd[01] o m2 mii1txd[02] o m1 mii1txd[03] o l3 mii1txenp o n2 mii1txer o n1 miimdc o m3 miimdio i/o p2 oen o c5 memory and peripheral bus pciad[00] i/o ad22 pci bus pciad[01] i/o af23 pciad[02] i/o ae23 pciad[03] i/o af22 pciad[04] i/o ad23 pciad[05] i/o ae22 pciad[06] i/o ad20 pciad[07] i/o af21 pciad[08] i/o ad19 pciad[09] i/o af20 pciad[10] i/o ae20 pciad[11] i/o ad18 pciad[12] i/o af19 pciad[13] i/o ae19 pciad[14] i/o af18 pciad[15] i/o ad17 pciad[16] i/o ae12 pciad[17] i/o af11 pciad[18] i/o ad10 pciad[19] i/o ae11 pciad[20] i/o af10 signal name i/o type location signal category table 24 rc32438 alphabetical signal list (part 7 of 9)
54 of 59 may 25, 2004 idt 79rc32438 pciad[21] i/o ad9 pci bus pciad[22] i/o ae10 pciad[23] i/o af9 pciad[24] i/o af8 pciad[25] i/o ae8 pciad[26] i/o ad7 pciad[27] i/o af7 pciad[28] i/o ae7 pciad[29] i/o af6 pciad[30] i/o ad6 pciad[31] i/o ae6 pcicben[00] i/o ae21 pcicben[01] i/o ae18 pcicben[02] i/o af14 pcicben[03] i/o ad8 pciclk i ad12 pcidevseln i/o ae16 pciframen i/o ae15 pcigntn[00] i/o ad13 pcigntn[01] i/o ae24 pcigntn[02] i/o af24 pcigntn[03] i/o ad21 pciirdyn i/o ad14 pcilockn i/o ae17 pcipar i/o af17 pciperrn i/o ad16 pcireqn[00] i/o af13 pcireqn[01] i/o ad11 pcireqn[02] i/o ae14 pcireqn[03] i/o af12 pcirstn i/o ae13 pciserrn i/o af16 pcistopn i/o ad15 pcitrdyn i/o af15 rstn i/o a23 system rwn o b3 memory and peripheral bus signal name i/o type location signal category table 24 rc32438 alphabetical signal list (part 8 of 9)
55 of 59 may 25, 2004 idt 79rc32438 sck i/o w2 spi interface scl i/o af4 i 2 c sda i/o ad4 sdi i/o v2 spi interface sdo i/o v1 vcc core d13, d14, d15, k4, l4, l23, m4, m23, n4, n23, p23, ac13, ac14, ac15 vcc i/o, vcc si/o see table 21 for a listing of power pins. vcc pll vss see table 22 for a listing of ground pins. vss pll waitackn i b2 memory and peripheral bus signal name i/o type location signal category table 24 rc32438 alphabetical signal list (part 9 of 9)
56 of 59 may 25, 2004 idt 79rc32438 rc32438 pinout ? top view 12345678910111213141516 vss (ground) vcc i/o (power) a b vcc core (power) 17 18 19 20 21 22 23 24 25 26 c d e f g h j k l m n p r t u v w y aa ab ac ad ae af vcc si/o (power) vccpll vccpll vsspll vsspll
57 of 59 may 25, 2004 idt 79rc32438 rc32438 package drawing ? 416-pin bga
58 of 59 may 25, 2004 idt 79rc32438 rc32438 package drawing ? page two
59 of 59 may 25, 2004 idt 79rc32438 corporate headquarters 2975 stender way santa clara, ca 95054 for sales: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com for tech support: email: rischelp@idt.com phone: 408-492-8208 ordering information valid combinations 79RC32K438 -200bb, 233bb, 266bb, 300bb 416-pin bga package, commercial temperature 79RC32K438 -200bbi, 233bbi 416-pin bga package, industrial temperature 79rcxx yy xxxx 999 a a operating voltage device type speed package temp range/ process k 200 blank commercial temperature (0c to +70c ambient) 200 mhz pipeline clk 1.2v +/- 0.1v core voltage (200/233 ) integrated core processor product type 79rc32 32-bit embedded microprocessor 416-pin bga bb 233 233 mhz pipeline clk 438 i industrial temperature (-40 c to +85 c ambient) 266 266 mhz pipeline clk 1.3v+/- 0.1v core voltage (266/300) 300 300 mhz pipeline clk

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